T89C51RD2-RDUC-L View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

T89C51RD2-RDUC-L

0 to 40 MHz Flash Programmable 8-bit Microcontroller

Atmel Corporation 

T89C51RD2

Fosc /12

Fosc / 4

T0 OVF

P1.2

To PCA

modules

overflow

It

CH

CL

16 bit up/down counter

CIDL WDTE

CPS1 CPS0 ECF

CMOD

0xD9

Idle

CF CR

CCF4 CCF3 CCF2 CCF1 CCF0

CCON

0xD8

Figure 7. PCA Timer/Counter

CMOD

Address 0D9H

Symbol

CIDL

WDTE

-

CPS1

CPS0

ECF

Table 7. CMOD: PCA Counter Mode Register

CIDL WDTE

-

-

-

CPS1 CPS0 ECF

Reset value

0

0

X

X

X

0

0

0

Function

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during

idle Mode. CIDL = 1 programs it to be gated off during idle.

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.

WDTE = 1 enables it.

Not implemented, reserved for future use.a

PCA Count Pulse Select bit 1.

PCA Count Pulse Select bit 0.

CPS1 CPS0 Selected PCA input.b

0

0 Internal clock fosc/12 ( Or fosc/6 in X2 Mode).

0

1 Internal clock fosc/4 ( Or fosc/2 in X2 Mode).

1

0 Timer 0 Overflow

1

1 External clock at ECI/P1.2 pin (max rate = fosc/ 8)

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an

interrupt. ECF = 0 disables that function of CF.

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

b. fosc = oscillator frequency

The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 7).

• The CIDL bit which allows the PCA to stop during idle mode.

• The WDTE bit which enables or disables the watchdog function on module 4.

23

Rev. F - 15 February, 2001

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