Fosc / 4
16 bit up/down counter
CPS1 CPS0 ECF
CCF4 CCF3 CCF2 CCF1 CCF0
Figure 7. PCA Timer/Counter
Table 7. CMOD: PCA Counter Mode Register
CPS1 CPS0 ECF
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
Not implemented, reserved for future use.a
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1 CPS0 Selected PCA input.b
0 Internal clock fosc/12 ( Or fosc/6 in X2 Mode).
1 Internal clock fosc/4 ( Or fosc/2 in X2 Mode).
0 Timer 0 Overflow
1 External clock at ECI/P1.2 pin (max rate = fosc/ 8)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
b. fosc = oscillator frequency
The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 7).
• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
Rev. F - 15 February, 2001