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T89C51RD2-DDFC-L View Datasheet(PDF) - Atmel Corporation

Part Name
Atmel Corporation Atmel
T89C51RD2-DDFC-L Datasheet PDF : 86 Pages
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0 to 40MHz Flash Programmable 8-bit Microcontroller
1. Description
ATMEL Wireless and Microcontrollers T89C51RD2 is
high performance CMOS Flash version of the 80C51
CMOS single chip 8-bit microcontroller. It contains a
64 Kbytes Flash memory block for program and for data.
The 64 Kbytes Flash memory can be programmed either
in parallel mode or in serial mode with the ISP capability
or with software. The programming voltage is internally
generated from the standard VCC pin.
The T89C51RD2 retains all features of the ATMEL
Wireless and Microcontrollers 80C52 with 256 bytes of
internal RAM, a 7-source 4-level interrupt controller and
three timer/counters.
In addition, the T89C51RD2 has a Programmable
Counter Array, an XRAM of 1024 bytes, an EEPROM
of 2048 bytes, a Hardware Watchdog Timer, a more
versatile serial channel that facilitates multiprocessor
communication (EUART) and a speed improvement
mechanism (X2 mode). Pinout is either the standard 40/
44 pins of the C52 or an extended version with 6 ports
in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
The T89C51RD2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
The added features of the T89C51RD2 makes it more
powerful for applications that need pulse width
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
2. Features
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports (or 6 in 64/68 pins packages)
Three 16-bit timer/counters
256 bytes scratch pad RAM
7 Interrupt sources with 4 priority levels
ISP (In System Programming) using standard VCC
power supply.
Boot FLASH contains low level FLASH
programming routines and a default serial loader
High-Speed Architecture
40 MHz in standard mode
20 MHz in X2 mode (6 clocks/machine cycle)
64K bytes on-chip Flash program / data Memory
Byte and page (128 bytes) erase and write
10k write cycles
On-chip 1024 bytes expanded RAM (XRAM)
Software selectable size (0, 256, 512, 768, 1024
768 bytes selected at reset for T87C51RD2
Dual Data Pointer
Variable length MOVX for slow RAM/peripherals
Improved X2 mode with independant selection for
CPU and each peripheral
2 k bytes EEPROM block for data storage
100K Write cycle
Programmable Counter Array with:
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
Asynchronous port reset
Full duplex Enhanced UART
Low EMI (inhibit ALE)
Hardware Watchdog Timer (One-time enabled with
Power control modes:
Idle Mode.
Power-down mode.
Rev. F - 15 February, 2001
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