6.3. Expanded RAM (XRAM)
The T89C51RD2 provide additional Bytes of random access memory (RAM) space for increased data parameter
handling and high level language usage.
T89C51RD2 devices have expanded RAM in external data space; Maximum size and location are described in Table 4.
Table 4. Description of expanded RAM
The T89C51RD2 has internal data memory that is mapped into four separate segments.
The four segments are:
• 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
• 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
• 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.
• 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit
cleared in the AUXR register. (See )
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed
by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they
have the same address, but are physically separate from SFR space.
FF or 3FF
direct or indirect
0100 or 0400
Figure 4. Internal and External Data Memory Address
When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the
upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR
at location 0A0H (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0,
# data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
Rev. F - 15 February, 2001