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T89C51RD2-DDFC-L View Datasheet(PDF) - Atmel Corporation

Part Name
Description
Manufacturer
T89C51RD2-DDFC-L
Atmel
Atmel Corporation Atmel
T89C51RD2-DDFC-L Datasheet PDF : 86 Pages
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T89C51RD2
6. Enhanced Features
In comparison to the original 80C52, the T89C51RD2 implements some new features, which are:
The X2 option.
The Dual Data Pointer.
The extended RAM.
The Programmable Counter Array (PCA).
The Watchdog.
The 4 level interrupt priority system.
The power-off flag.
The ONCE mode.
The ALE disabling.
Some enhanced features are also located in the UART and the timer 2.
6.1. X2 Feature and Clock Generation
The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
6.1.1. Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
XTAL1
FXTAL
2
XTAL1:2
0
1
X2
FOSC
CKCON reg
state machine: 6 clock cycles.
CPU control
Figure 1. Clock Generation Diagram
Rev. F - 15 February, 2001
10
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