S3C1840 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S3C1840

4-bit single-chip CMOS microcontroller

Samsung 

S3C1840

HALT MODE

The HALT mode is used to reduce power consumption by stopping the clock and holding the states of all internal

operations fixed. This mode is very useful in battery-powered instruments. It also holds the controller in wait

status for external stimulus to start some event. The S3C1840 can be halted by programming the P2.12 pin high,

and by forcing P0 input pins (P0.0-P0.3) to high and P1 input pins (P1.0-P1.3) to high, concurrently (See Figure

1-16). When in HALT mode, the internal circuitry does not receive any clock signal, and all P2, P3 output pins

become low states. However, P2.1 and P2.6 pins retain their programmed values until the device is re-started as

follows:

• Forcing any P0 and P1 input pins to low : system reset occurs and it continues to operate from the reset

address.

An oscillation stabilization time of 13 msec in fxx = 455 kHz crystal oscillation is needed for stability (See Figure

1-17).

VDD

P0.3-P0.0

4

P1.3-P1.0

4

Internal P2.12

Internal HALT

System reset

Figure 1-16. Block Diagram of HALT Logic

HALT

X'tal

HALT mode

Normal Mode

HALT mode

13 msec (Minimum) 120 µsec (Typical)

Figure 1-17. Release Timing for HALT or RESET to Normal Mode in Crystal Oscillation

1-16

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