RT8859M View Datasheet(PDF) - Richtek Technology

Part Name

Description

Manufacturer

RT8859M

Multi-Phase PWM Controller for CPU Core Power Supply

Richtek Technology 

RT8859M

continuous cycles, the OCP latch counter will be reset.

When OCP is triggered by the CORE VR, the AXG VR

will also enter soft shut down sequence.

If inductor DCR is used as the current sense component,

temperature compensation is recommended for proper

protection under all conditions. Figure 15 shows a typical

OCP setting with temperature compensation.

VCC

ROC1a

NTC

OCSET

ROC1b

ROC2

Figure 15. OCP Setting with Temperature Compensation

Usually, ROC1a is selected to be equal to the thermistor's

nominal resistance at room temperature. Ideally, assume

VOCSET has the same temperature coefficient as RSENSE

(Inductor DCR) :

VOCSET, HOT = RSENSE, HOT

VOCSET, COLD RSENSE, COLD

(30)

According to the basic circuit calculation, we can get

VOCSET at any temperature:

VOCSET, T°C

= VCC

x

ROC1a

ROC2

/ /RNTC, T°C + ROC1b + ROC2

(31)

Re-write (31) from (30) to get VOCSET at room temperature

ROC1a // RNTC, COLD + ROC1b + ROC2

ROC1a // RNTC, HOT + ROC1b + ROC2

=

RSENSE, HOT

RSENSE, COLD

(32)

VOCSET, 25°C =

VCC

x

ROC1a

ROC2

/ /RNTC, 25°C + ROC1b

+ ROC2

(33)

Solving (32) and (33) yields ROC1b and ROC2

ROC2 =

α x REQU, HOT − REQU, COLD + (1− α) x REQU, 25°C

VCC

x (1− α)

VOCSET, 25°C

(34)

Copyright ©2012 Richtek Technology Corporation. All rights reserved.

www.richtek.com

40

ROC1b =

(α − 1) x ROC2 + α x REQU, HOT − REQU, COLD (35)

(1− α)

where

α=

RSENSE, HOT

RSENSE, COLD

=

DCR25°C x [1+ 0.00393 x (THOT − 25)]

DCR25°C x [1+ 0.00393 x (TCOLD − 25)]

(36)

REQU, T°C = ROC1a // RNTC, T°C

(37)

Over Voltage Protection (OVP)

The over voltage protection circuit of the CORE VR

monitors the output voltage via the ISEN1N pin after POR.

The supported maximum operating VID of the VR (V(MAX))

is stored in the VOUT_Max register. Once VISEN1N

exceeds “V(MAX) + 150mV”, OVP is triggered and latched.

The CORE VR will try to turn on low side MOSFETs and

turn off high side MOSFETs of all active phases of the

CORE VR to protect the CPU. When OVP is triggered by

the CORE VR, the AXG VR will also enter soft shut down

sequence. A 1μs delay is used in OVP detection circuit

to prevent false trigger. Note that if OFS pin is higher than

0.9V before power up, OVP will trigger at “VMAX +850mV”.

Negative Voltage Protection (NVP)

During OVP latch state, the CORE VR also monitors the

ISEN1N pin for negative voltage protection. Since the OVP

latch will continuously turn on all low side MOSFETs of

the CORE VR, the CORE VR may suffer negative output

voltage. As a consequence, when the ISEN1N voltage

drops below −0.05V after triggering OVP, the CORE VR

will trigger NVP to turn off all low side MOSFETs of the

CORE VR while the high side MOSFETs still remains off.

After triggering NVP, if the output voltage rises above 0V,

the OVP latch will restart to turn on all low side MOSFETs.

Therefore, the output voltage may travel between 0V and

−0.05V due to OVP latch and NVP triggering. The NVP

function will be active only after OVP is triggered. A 1μs

delay is used in NVP detection circuit to prevent false

trigger.

Under Voltage Protection (UVP)

The CORE VR implements under voltage protection of

VOUT,CORE. If ISEN1N is less than the internal reference

is a registered trademark of Richtek Technology Corporation.

DS8859M-05 July 2012

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