PIC16LCR61-10/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LCR61-10/SO Datasheet PDF : 336 Pages
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Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set for the synchro-
nous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output. If
the SS pin is taken low without resetting SPI mode,
the transmission will continue from the point at
which it was taken high. External pull-up/ pull-down
resistors may be desirable, depending on the applica-
tion.
Note:
When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note:
If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 11-11: SPI MODE TIMING, MASTER MODE (PIC16C66/67)
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
SDI (SMP = 0)
SDI (SMP = 1)
SSPIF
bit7
bit7
FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C66/67)
SS (optional)
bit0
bit0
bit0
SCK (CKP = 0)
SCK (CKP = 1)
SDO
SDI (SMP = 0)
SSPIF
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
bit0
© 1997 Microchip Technology Inc.
DS30234D-page 93
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