PCD5096H View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

PCD5096H

Universal codec

Philips Electronics 

Philips Semiconductors

Universal codec

Preliminary specification

PCD5096

7 FUNCTIONAL DESCRIPTION

7.1 General

The PCD5096 is a universal codec designed for use in

digital terminal equipment. It connects two PSTN lines to a

digital interface (IOM-2), thus covering a wide application

area. Echo cancellation is performed on both PSTN lines

by an on-chip DSP. Hands-free speaker phone

functionality is also provided by sacrificing one PSTN line

connection. The chip is controlled by an external

microcontroller via a high bit rate I2C-bus interface.

Figure 1 shows the block diagram of the PCD5096.

The different functional blocks operate more or less

autonomously and communicate with each other via the

System Data RAM (SDR). Each block has access to the

SDR via an internal system bus. Access to this bus is

controlled by the System Data RAM Controller (SDRC).

The IOM block connects to a n × 256 kbits/s digital

interface (IOM-2 interface) and also supports interfacing to

DTAM speech compression ICs. The IOM block stores

and fetches speech data into/from the SDR using internal

addressing logic.

The DSP block is the link between the data in the SDR

stored/fetched by the IOM block on one hand, and the

analog front-end on the other hand. The basic functions of

the DSP are data filtering, local echo cancelling, network

echo suppressing, A-law coding and decoding according

to the G.711 CCITT recommendations, dial tone detection

and generation, DTMF generation, side-tone, automatic

volume control, automatic gain control, double talk

detection and conference call.

Data processed by the DSP goes to and comes from two

independent codecs interfacing to the PSTN lines.

The codecs comply with the G.714 specifications and

handle the PCM coding and decoding of speech signals.

They perform the analog and high speed digital speech

processing functions: analog bitstream A/D and D/A

conversion, analog filtering and amplification, digital

decimation filtering and noise shaping. Both codecs

should be connected to a local line or to a PSTN line, but

one codec also supports a corded handset and hands-free

speaker and microphone.

The control of the entire chip is done via the I2C-bus block

by writing to the SDR or to special control registers. In this

way the DSP and the IOM operation modes can be set, as

well as some analog parameters in the two codecs.

The PCD5096 has two general purpose programmable I/O

pins controlled by two special registers (direction and

state). These two special registers are accessible via the

I2C-bus interface or by the on-chip DSP. A typical

application is the generation of interrupts by the DSP,

indicating that DTMF tones were detected.

The timing for the whole chip is generated in the Timing

Control Block (TICB). The system clock (20.736 MHz) is

delivered by a PLL which triples the input clock frequency.

7.2 Clocking

The universal codec is designed to operate in a digital

cordless telephone system, for example together with a

PCD5093 baseband controller. To save the expense of

having to provide each universal codec with a separate

crystal, a common clock is provided by the master

controller. In the current generation of the Philips DECT

baseband controllers this clock is GP_CLK7, a 6.912 MHz

clock output derived from the 13.824 MHz crystal

oscillator. GP_CLK7 must therefore be used as the input

clock for the universal codec. GP_CLK7 is enabled during

a reset of the PCD5093 and when either the Burst Mode

Logic or codec are turned on (see PCD5093 data sheet).

In order to meet the DSP processing requirements for the

various applications an on-chip PLL is used to generate a

system clock which is triple the input clock frequency

(20.736 MHz).

7.3 Reset and power-down strategy

The universal codec must be reset at power-up.

The RESET input must remain HIGH until the CLK input is

active (toggling) and stable. After releasing the RESET

input, an additional 1024 CLK periods (≈150 µs at

6.912 MHz) must elapse before starting to program the

chip via the I2C-bus interface. This must be done after

every RESET pulse. The minimum duration of a RESET

pulse is one CLK period. During reset, the I2C-bus and the

IOM-2 interface are inactive.

Entering the Power-down mode is achieved by resetting

the chip and holding the RESET input HIGH. This resets

the on-chip PLL and stops the system clock. The user

must ensure that the IOM-2 interface is deactivated and

the I2C-bus idle before resetting the chip in order not to

interrupt any transaction on these two interfaces. Note that

stopping the CLK input is only allowed while the RESET

input is HIGH. To exit the Power-down mode the RESET

input is set LOW and after 1024 CLK periods (≈150 µs at

6.912 MHz) have elapsed normal operation can be

resumed.

1997 Jan 22

10

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