M74HC40102TTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M74HC40102TTR Datasheet PDF : 16 Pages
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M74HC40102
8 STAGE PRESETTABLE
SYNCHRONOUS DOWN COUNTER
s HIGH SPEED :
fMAX = 38MHz (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 40102
DESCRIPTION
The M74HC40102 is an high speed CMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTER fabricated with silicon gate
C2MOS technology.
The HCF40102 consists of an 8 stage
synchronous down counter with a single output
which is active when the internal count is zero.
The HC40102 is configured as two cascaded 4-bit
BCD counters. This device has control inputs for
enabling or disabling the clock, for clearing the
counter to its maximum count, and for presetting
the counter either synchronously or
asynchronously. All control inputs and the
CARRY-OUT / ZERO DETECT output are active
low logic. In normal operation the counter is
decremented by one count on each positive
PIN CONNECTION AND IEC LOGIC SYMBOLS
DIP
SOP
TSSOP
ORDER CODES
PACKAG
E
TUBE
T&R
DIP
SOP
TSSOP
M74HC40102B1R
M74HC40102M1R M74HC40102RM13TR
M74HC40102TTR
transition of the CLOCK. Counting is inhibited
when the CARRY-IN / COUNTER ENABLE (CI/
CE) input is high. The CARRY-OUT /
ZERO-DETECT (CO/ZD) output goes low when
the count reaches zero if the CI/CE input is low,
and remains low for one full clock period. When
the SYNCHRONOUS PRESET-ENABLE (SPE)
input is low, data at the J input is clocked into the
counter on the next positive clock transition
regardless of the state of the CI/CE input.
When the ASYNCHRONOUS PRESET-ENABLE
(APE) input is low, data at the J inputs is
asynchronously forced into the counter regardless
of the state of the SPE CI/CE or CLOCK inputs. J
input J0-J7 represent two 4-bit BCD words. When
the CLEAR, CLR input is low, the counter is
September 2001
1/16
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