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MTV021N24 View Datasheet(PDF) - Unspecified

Part Name
Description
Manufacturer
MTV021N24
ETC
Unspecified ETC
MTV021N24 Datasheet PDF : 17 Pages
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MYSON
TECHNOLOGY
MTV021
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is config-
ured as the state diagram shown in Figure 3.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X ROW
format (c) 0, 1
0, 0 format (b)
0, 0
COL
c
X, X
COL
0, 1
ab X, X
1, X
X, X
DA
c
DA
ab
FIGURE 3. Transmission State Diagram
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as
Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = one horizontal line display time
TABLE 2. Repeat line weight of character
CH6 - CH0
CH6,CH5=11
CH6,CH5=10
CH6,CH5=0x
CH4=1
Repeat Line Weight
+18*3
+18*2
+18
+16
5/17
MTV021 Revision 5.0 6/29/1999
 

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