MAX149ACAP View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX149ACAP Datasheet PDF : 23 Pages
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+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
SYMBOL
CONDITIONS
tACQ
tDS
tDH
tDO Figure 1, MAX14_ _C/E
tDV Figure 1
tTR Figure 2
tCSS
tCSH
tCH
tCL
tSSTRB Figure 1
tSDV External clock mode only, Figure 1
tSTR External clock mode only, Figure 2
tSCK Internal clock mode only (Note 7)
MIN TYP MAX UNITS
1.5
μs
100
ns
0
ns
20
200
ns
240
ns
240
ns
100
ns
0
ns
200
ns
200
ns
240
ns
240
ns
240
ns
0
ns
Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300FVP-P.
Note 10: Guaranteed by design. Not subject to production testing.
Note 11: The MAX148 typically draws 400FA less than the values shown.
Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
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