MAX148ACAP View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX148ACAP

+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs

Maxim Integrated 

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

CS

SCLK

DIN

DOUT

SSTRB

1

8

15 1

8

15 1

S

CONTROL BYTE 0

S

CONTROL BYTE 1

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 0

S

CONTROL BYTE 2

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 1

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS

SCLK

DIN

DOUT

1

8

S

CONTROL BYTE 0

16

1

8

S

CONTROL BYTE 1

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 0

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

16

B9 B8 B7 B6

CONVERSION RESULT 1

CLOCK

MODE

SHDN

DIN

DOUT

SETS EXTERNAL

CLOCK MODE

SXXXXX11

10 + 2 DATA BITS

MODE

POWERED UP

EXTERNAL

EXTERNAL

SETS SOFTWARE

POWER-DOWN

SX XXXX 0 0

SETS EXTERNAL

CLOCK MODE

S XX XXX 1 1

10 + 2 DATA BITS

VALID

DATA

INVALID

DATA

SOFTWARE

POWER-DOWN

POWERED UP

HARDWARE

POWER-DOWN

POWERED UP

Figure 12a. Timing Diagram Power-Down Modes, External Clock

delay and maximum sample rate. In external compensa-

tion mode, power-up time is 20ms with a 4.7FF com-

pensation capacitor when the capacitor is initially fully

discharged. From fast power-down, startup time can be

eliminated by using low-leakage capacitors that do not

discharge more than ½ LSB while shut down. In power-

down, leakage currents at VREF cause droop on the

reference bypass capacitor. Figures 12a and 12b show

the various power-down sequences in both external and

internal clock modes.

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