M74HC4017 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M74HC4017 Datasheet PDF : 12 Pages
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M74HC4017
DECADE COUNTER/DIVIDER
s HIGH SPEED :
tPD = 21 ns (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4017
DESCRIPTION
The M74HC4017 is an high speed CMOS
DECADE COUNTER/DIVIDER fabricated with
silicon gate C2MOS technology.
The M74HC4017 is a 5-stage Johnson counter
with 10 decoded outputs. Each of the decoded
outputs is normally low and sequentially goes high
on the low to high transition of the clock input.
Each output stays high for one clock period of the
10 clock period cycle. The CARRY output goes
low to high after OUTPUT 10 goes low, and can
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
TSSOP
M74HC4017B1R
M74HC4017M1R M74HC4017RM13TR
M74HC4017TTR
be used in conjunction with the CLOCK ENABLE
(CKEN)to cascade several stages.
The CLOCK ENABLE input disables counting
when in the high state. A CLEAR (CLR) input is
also provided which when taken high sets all the
decoded outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/12
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