UT9Q512 View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
UT9Q512 Datasheet PDF : 15 Pages
| |||
Standard Products
QCOTSTM UT9Q512 512K x 8 SRAM
Data Sheet
February, 2003
FEATURES
q 20ns maximum (5 volt supply) address access time
q Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
q TTL compatible inputs and output levels, three-state
bidirectional data bus
q Typical radiation performance
- Total dose: 50krads
- >100krads(Si), for any orbit, using Aeroflex UTMC
patented shielded package
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section (cm2) per bit, 5.0E-9
-<1E-8 errors/bit-day, Adams to 90% geosynchronous
heavy ion
q Packaging options:
- 36-lead ceramic flatpack (weight 3.42 grams)
- 36-lead flatpack shielded (weight 10.77 grams)
q Standard Microcircuit Drawing 5962-00536
- QML T and Q compliant part
INTRODUCTION
The QCOTSTM UT9Q512 Quantified Commercial Off-the-
Shelf product is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable ( E),
an active LOW Output Enable (G), and three-state drivers.
This device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the devicei s accomplished by taking Chip Enable
one (E) input LOW and Write Enable (W) inputs LOW.
Data on the eight I/O pins (DQ0 through DQ7 ) is then written
into the location specified on the address pins (A0 through
A18). Reading from the device is accomplished by taking
Chip Enable one (E) and Output Enable (G) LOW while
forcing Write Enable (W) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed
in a high impedance state when the device is deselected (E)
HIGH), the outputs are disabled ( G HIGH), or during a write
operation (E LOWand W LOW).
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ0 -DQ7
Memory Array
1024 Rows
512x8 Columns
Data
Control
CLK
Gen.
I/O Circuit
Column Select
E
W
G
Figure 1. UT9Q512 SRAM Block Diagram
|
|
Share Link: 