A(18:0)
tAVAV
DQ(7:0)
Previous Valid Data
Assumptions:
1. E1 and G < VIL (max) and EZ and W > VIH (min)
tAXQX
Valid Data
tAVQV
Figure 3a. SRAM Read Cycle 1: Address Access
A(18:0)
E1 low or
E2 high
DQ(7:0)
tETQV
Assumptions:
1. G < VIL (max) and W > VIH (min)
tETQX
tEFQZ
DATA VALID
Figure 3b. SRAM Read Cycle 2: Chip Enable Access
A(18:0)
tAVQV
G
DQ(7:0)
tGLQX
Assumptions:
1. E1 < VIL (max) , E2 > and W > VIH (min)
tGLQV
DATA VALID
tGHQZ
Figure 3c. SRAM Read Cycle 3: Output Enable Access
8