5962F-0323502VUA View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F-0323502VUA

UT8R512K8 512K x 8 SRAM

Aeroflex UTMC 

WRITE CYCLE

A combination of W and E1 less than VIL(max) and E2 greater

than VIH(min) defines a write cycle. The state of G is a “don’t

care” for a write cycle. The outputs are placed in the high-

impedance state when either G is greater than VIH(min), or

when W is less than VIL(max).

Write Cycle 1, the Write Enable-controlled Access in Figure

4a, is defined by a write terminated by W going high, with E1

and E2 still active. The write pulse width is defined by tWLWH

when the write is initiated by W, and by tETWH when the write

is initiated by E1 or E2. Unless the outputs have been

previously placed in the high-impedance state by G, the user

must wait tWLQZ before applying data to the nine bidirectional

pins DQ(7:0) to avoid bus contention.

Write Cycle 2, the Chip Enable-controlled Access in Figure

4b, is defined by a write terminated by either of E1 or E2 going

inactive. The write pulse width is defined by tWLEF when the

write is initiated by W, and by tETEF when the write is initiated

by either E1or E2 going active. For the W initiated write, unless

the outputs have been previously placed in the high-impedance

state by G, the user must wait tWLQZ before applying data to

the eight bidirectional pins DQ(7:0) to avoid bus contention.

OPERATIONAL ENVIRONMENT

The UT8R512K8 SRAM incorporates special design and

layout features which allows operation in a limited

environment.

Table 2. Operational Environment

Design Specifications1

Total Dose

300K

rad(Si)

Heavy Ion

Error Rate2

8.9x10-10 Errors/Bit-Day

Notes:

1. The SRAM is immune to latchup to particles >100MeV-cm2/mg.

2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of

Aluminum.

Supply Sequencing

No supply voltage sequencing is required between VDD1 and

VDD2.

3

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