5962F-0323502QUC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F-0323502QUC

UT8R512K8 512K x 8 SRAM

Aeroflex UTMC 

Aeroflex Colorado Springs Application Note

AN-MEM-002

2.1.1 Chip Enable-Controlled Read Cycle

The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and

the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0)

is accessed and appears at the data outputs DQ(7:0).

A(18:0)

E1 low or

E2 high

DQ(7:0)

tETQV

Assumptions:

1. G < VIL (max) and W > VIH (min)

tETQX

tEFQZ

DATA VALID

Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that

addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum.

SRAM Read Cycle 2: Chip Enable Access

2.1.1 Output Enabled-Controlled Read Cycle

The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the

addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.

A(18:0)

tAVQV

G

DQ(7:0)

tGLQX

Assumptions:

1. E1 < VIL (max) , E2 > and W > VIH (min)

tGLQV

DATA VALID

tGHQZ

SRAM Read Cycle 3: Output Enable Access

3.0 Low Power Read Architecture Timing Consideration

The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in

applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input

signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns

between all of the read triggering activities is sufficient to start another read cycle.

Creation Date: 8/19/11

Page 3 of 5

Modification Date: 4/24/13

Share Link: