5962-9960601TUC View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962-9960601TUC
Aeroflex UTMC
5962-9960601TUC Datasheet PDF : 16 Pages
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PIN NAMES
A(18:0) Address
DQ(7:0) Data Input/Output
E
Chip Enable
W Write Enable
G
Output Enable
VDD Power
VSS
Ground
A18
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
VD D
9
V SS
10
A3
11
A2
12
A1
13
A0
14
DQ0
15
DQ1
16
DQ2
17
DQ3
18
36
NC
35
A15
34
A17
33
W
32
A13
31
A8
30
A9
29
A11
28
VS S
27
VD D
26
G
25
A10
24
E
23
DQ7
22
DQ6
21
DQ5
20
DQ4
19
NC
Figure 2a. UT7Q512 100ns SRAM Shielded
Package Pinout (36)
A18
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
13
DQ1
14
DQ2
15
V SS
16
32
VD D
31
A15
30
A17
29
W
28
A13
27
A8
26
A9
25
A11
24
G
23
A10
22
E
21
DQ7
20
DQ6
19
DQ5
18
DQ4
17
DQ3
Figure 2b. UT7Q512 100ns SRAM
Package Pinout (32)
DEVICE OPERATION
The UT7Q512 has three control inputs called Enable 1 ( E), Write
Enable ( W), and Output Enable (G); 19 address inputs, A(18:0);
and eight bidirectional data lines, DQ(7:0).The E Device Enable
controls device selection, active, and standby modes. Asserting
E enables the device, causes IDD to rise to its active value, and
decodes the 19 address inputs to select one of 524,288 words in
the memory. W controls read and write operations. During a
read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
W
X1
X
E I/O Mode Mode
1 3-state
Standby
X
0
0 Data in Write
1
1
0 3-state
Read2
0
1
0 Data out Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min), G and E less than
VIL (max) defines a read cycle. Read access time is measured
from the latter of Device Enable, Output Enable, or valid address
to valid data output.
SRAM read Cycle 1, the Address Access in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified tAVQV is satisfied. Outputs remain
active throughout the entire cycle. As long asDevice Enable and
Output Enable are active, the address inputs may change at a
rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable-Controlled Access in
figure 3b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable-Controlled Access in
figure 3c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
2
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