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M1025-1Z-125.0000 View Datasheet(PDF) - Integrated Circuit Systems

Part Name
Description
Manufacturer
M1025-1Z-125.0000
ICST
Integrated Circuit Systems ICST
M1025-1Z-125.0000 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O Configuration
Ground
Description
Power supply ground connections.
4
9
5
8
6
7
11, 19, 33
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
Input
Output
Input
Power
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
Power supply connection, connect to +3.3V.
Automatic/manual reselection mode for clock input:
12
AUTO
Input
Internal pull-down resistor1
Logic 1 automatic reselection upon clock failure
(non-revertive)
Logic 0 manual selection only (using REF_SEL)
Reference Acknowledgement pin for input mux state; outputs
13
REF_ACK
Output
the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
15
16
FOUT
nFOUT
Output No internal terminator Clock output pair. Differential LVPECL (CML, LVDS available).
17
P_SEL1
18
P_SEL0
Internal pull-down resistor1
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT), on pg. 4.
20
21
nDIF_REF1
DIF_REF1
Input
Biased to Vcc/2 2
Reference clock input pair 1. Differential LVPECL or LVDS.
Internal pull-down resistor1 Resistor bias on inverting terminal supports TTL or LVCMOS.
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
DIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Internal pull-down resistor 1 Resistor bias on inverting terminal supports TTL or LVCMOS.
25
NC
No internal connection.
27
28
29
MR_SEL3
MR_SEL2
MR_SEL0
M and R divider value selection. LVCMOS/ LVTTL.
Input Internal pull-down resistor1 See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
30
MR_SEL1
31
LOL
Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
32
NBW
Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
34, 35, 36
DNC
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 11.
Table 2: Pin Descriptions
Note 2: Biased toVcc/2, with 50kto Vcc and 50kto ground. See Differential Inputs Biased to VCC/2 on pg. 11.
Note 3: See LVCMOS Output in DC Characteristics on pg. 11.
M1025/26 Datasheet Rev 1.0
2 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400
 

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