DK-LM3S817 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

DK-LM3S817

Microcontroller

Unspecified 

JTAG Interface

5 JTAG Interface

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and

Boundary Scan Architecture for digital integrated circuits and provides a standardized serial

interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data

Registers (DR) can be used to test the interconnections of assembled printed circuit boards and

obtain manufacturing information on the components. The JTAG Port also provides a means of

accessing and controlling design-for-test features such as I/O pin observation and control, scan

testing, and debugging.

The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is

transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of

this data is dependent on the current state of the TAP controller. For detailed information on the

operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test

Access Port and Boundary-Scan Architecture.

The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is

implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions

select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The

multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for

the ARM, LMI, and unimplemented JTAG instructions.

The JTAG module has the following features:

„ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

„ Four-bit Instruction Register (IR) chain for storing JTAG instructions

„ IEEE standard instructions:

– BYPASS instruction

– IDCODE instruction

– SAMPLE/PRELOAD instruction

– EXTEST instruction

– INTEST instruction

„ ARM additional instructions:

– APACC instruction

– DPACC instruction

– ABORT instruction

„ Integrated ARM Serial Wire Debug (SWD)

See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG

controller.

46

May 4, 2007

Preliminary

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