LM3S801 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

LM3S801

Microcontroller

Unspecified 

JTAG Interface

5.2.1

5.2.1.1

5.2.1.2

5.2.1.3

JTAG Interface Pins

The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and

their associated reset state are given in Table 5-1. Detailed information on each pin follows.

Table 5-1. JTAG Port Pins Reset State

Pin Name

TRST

TCK

TMS

TDI

TDO

Data

Direction

Input

Input

Input

Input

Output

Internal

Pull-Up

Enabled

Enabled

Enabled

Enabled

Enabled

Internal

Pull-Down

Disabled

Disabled

Disabled

Disabled

Disabled

Drive

Strength

N/A

N/A

N/A

N/A

2-mA driver

Drive Value

N/A

N/A

N/A

N/A

High-Z

Test Reset Input (TRST)

The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG

TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to

the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller

enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default

instruction, IDCODE.

By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the

pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains

enabled on PB7/TRST; otherwise JTAG communication could be lost.

Test Clock Input (TCK)

The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate

independently of any other system clocks. In addition, it ensures that multiple JTAG TAP

controllers that are daisy-chained together can synchronously communicate serial test data

between components. During normal operation, TCK is driven by a free-running clock with a

nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of

time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in

the JTAG Instruction and Data Registers is not lost.

By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no

clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down

resistors can be turned off to save internal power as long as the TCK pin is constantly being driven

by an external source.

Test Mode Select (TMS)

The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge

of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is

entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1

expects the value on TMS to change on the falling edge of TCK.

Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the

Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG

Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can

be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state

machine can be seen in its entirety in Figure 5-2 on page 46.

44

October 8, 2006

Preliminary

Share Link: