LM3S801 View Datasheet(PDF) - Unspecified
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LM3S801 Datasheet PDF : 397 Pages
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LM3S801 Data Sheet
About This Document
This data sheet provides reference information for the LM3S801 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation
CD or from the Luminary Micro web site at www.luminarymicro.com:
ARM® Cortex™-M3 Technical Reference Manual
CoreSight™ Design Kit Technical Reference Manual
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 0-1.
Table 0-1. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
bit
bit field
offset 0xnnn
APB registers are indicated in uppercase bold. For example,
PBORCTL is the Power-On and Brown-Out Reset Control register. If
a register name contains a lowercase n, it represents more than one
register. For example, SRCRn represents any (or all) of the three
Software Reset Control registers: SRCR0, SRCR1, and SRCR2.
A single bit in a register.
Two or more consecutive and related bits.
A hexadecimal increment to a register’s address, relative to that
module’s base address as specified in Table 3-1, "Memory Map," on
page 37.
October 8, 2006
19
Preliminary
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