LM3S801 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
LM3S801 Datasheet PDF : 397 Pages
| |||
List of Registers
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Control (WDTCTL), offset 0x008............................................................................ 184
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 185
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 186
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 187
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 188
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 189
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 190
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 191
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 192
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 193
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 194
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 195
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 196
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 197
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 198
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 199
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 200
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 201
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 202
Register 1: UART Data (UARTDR), offset 0x000 ...................................................................................... 209
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 211
Register 3: UART Flag (UARTFR), offset 0x018 ....................................................................................... 213
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 215
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 216
Register 6: UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 217
Register 7: UART Control (UARTCTL), offset 0x030................................................................................. 219
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 220
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 221
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 223
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 224
Register 12: UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 225
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 226
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 227
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 228
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 229
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 230
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 231
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 232
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 233
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 234
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 235
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 236
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 237
Synchronous Serial Interface (SSI) ............................................................................................. 238
Register 1: SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 250
Register 2: SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 252
Register 3: SSI Data (SSIDR), offset 0x008 .............................................................................................. 254
Register 4: SSI Status (SSISR), offset 0x00C ........................................................................................... 255
14
October 8, 2006
Preliminary
|
|
Share Link: 