LM3S2965 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

LM3S2965

Microcontroller

Unspecified 

2.1 Block Diagram

Figure 2-1. CPU Block Diagram

LM3S2965 Microcontroller

Nested

Vectored

Interrupt

Controller

Interrupts

Sleep

Debug

CM3 Core

Instructions Data

Memory

Protection

Unit

ARM

Cortex-M3

Serial

Wire

Output

Trace

Trace Port

Port (SWO)

Interface

Unit

Serial Wire JTAG

Debug Port

Flash

Patch and

Breakpoint

Private Peripheral

Bus

(internal)

Adv. High-

Perf. Bus

Access Port

Data Instrumentation

Watchpoint Trace Macrocell

and Trace

Private

Peripheral

Bus

(external)

ROM

Table

Bus

Matrix

Adv. Peripheral

Bus

I-code bus

D-code bus

System bus

2.2

2.2.1

Functional Description

Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an

ARM Cortex-M3 in detail. However, these features differ based on the implementation.

This section describes the Stellaris® implementation.

Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 39. As

noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are

flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested

Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.

Serial Wire and JTAG Debug

Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant

Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the

ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices.

The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the

CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.

November 30, 2007

39

Preliminary

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