LM3S2965 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

LM3S2965

Microcontroller

Unspecified 

Architectural Overview

1.4.7

1.4.7.1

1.4.7.2

1.4.7.3

1.4.7.4

1.4.8

be read by the controller instruction fetch mechanism, protecting the contents of those blocks from

being read by either the controller or by a debugger.

Additional Features

Memory Map (see page 44)

A memory map lists the location of instructions and data in memory. The memory map for the

LM3S2965 controller can be found in “Memory Map” on page 44. Register addresses are given as

a hexadecimal increment, relative to the module's base address as shown in the memory map.

The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory

map.

JTAG TAP Controller (see page 49)

The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the

Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG

data registers can be used to test the interconnects of assembled printed circuit boards, obtain

manufacturing information on the components, and observe and/or control the inputs and outputs

of the controller during normal operation. The JTAG port provides a high degree of testability and

chip-level access at a low cost.

The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is

transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of

this data is dependent on the current state of the TAP controller. For detailed information on the

operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test

Access Port and Boundary-Scan Architecture.

The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3

core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG

instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary

Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has

comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.

System Control and Clocks (see page 60)

System control determines the overall operation of the device. It provides information about the

device, controls the clocking of the device and individual peripherals, and handles reset detection

and reporting.

Hibernation Module (see page 121)

The Hibernation module provides logic to switch power off to the main processor and peripherals,

and to wake on external or time-based events. The Hibernation module includes power-sequencing

logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt

signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used

for saving state during hibernation.

Hardware Details

Details on the pins and package can be found in the following sections:

■ “Pin Diagram” on page 517

■ “Signal Tables” on page 518

36

November 30, 2007

Preliminary

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