5962G9684501QXC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962G9684501QXC

4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag

Aeroflex UTMC 

tWC

Address

CE

R/ W

Data in

tSCE

tAW

tH A

tPWE

tSA

tSD

tHD

DATA VALID

OE

Data out

tHZOE

HIGH IMPE DANCE

tLZOE

Assumptions:

1. The internal write time of memory is defined by the overlap of CE

LOW and R/W LOW. Both signals must be LOW to initiate a write,

and either signal can terminate a write by going HIGH. The data input

set-up and hold timing should be referenced to the rising edge of the

signal that terminates the write.

2. If OE is LOW during a R/W controlled write cycle, the write pulse

width must be the larger of tPWE or (tHZWE + tSD ) to allow the I/O

drivers to turn off and data to be placed on the bus for the required t SD.

If OE is HIGH during a R/W controlled write cycle (as in this exam-

ple), this requirement does not apply and the write pulse can be as

short as the specified tPWE.

3. R/W must be HIGH during all address transactions.

Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)

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