IP101A View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
IP101A Datasheet PDF : 36 Pages
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Register Descriptions (continued)
IP101A LF
Data Sheet
Bit
Name
Description/Usage
Register 16 : PHY Spec. Control Register
15 Debug Mode
0 = IP101A LF operates at normal mode
1 = IP101A LF operates at debug mode
(Note: the functionalities of bit 16:<14:12>, and 16:<4:0>
depend on the setting of this bit 16:<15>)
14:12 Reserved
11 Auto MDIX Off
Set high to disable the automatic switch of MDI and MDI-X
modes. If AN is disabled by setting pin37=0 during power
up, this bit will be set to 1 (Auto-MDIX off) automatically.
Setting Reg0.12=1 will re-activate AN, in this case, if user
needs Auto-MDIX function, this bit should be set to 0. For
details, please refer to section 7 Auto-MDIX function
description.
10 Heart Beat
Enable
Heart beat function enable at 10Base-T
9 Jabber Enable Jabber function enable at 10Base-T
8 Far-End Fault
Enable/Disable
To enable or disable the functionality of Far-End Fault
Mode
Enable Disable
100Base-TX
1
0
7 Analog Power Set high to disable the power saving during auto-negotiation
Saving Disable
6 Reserved
5 Bypass DSP
reset
Set high to bypass the reset DSP mechanism in PCS
sub-layer
4:3 Reserved
2 Repeater Mode Set high to put IP101A LF into repeater mode
1 APS Mode
Set high to enable Auto Power Saving mode
0 Analog Off
Set high to power down analog transceiver
Default value
(h): 0000
0, R/W
0, RO
0, R/W
0, R/W
0, R/W
0, R/W
0, R/W
0, RO
0, R/W
0, RO
0, R/W
0, R/W
0, R/W
Copyright © 2004, IC Plus Corp.
19/36
Oct 22, 2007
IP101A LF-DS-R12
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