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IDT70261 View Datasheet(PDF) - Integrated Device Technology

Part Name
Description
Manufacturer
IDT70261
IDT
Integrated Device Technology IDT
IDT70261 Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
A0-A2
SEM
I/O0
R/W
VALID ADDRESS
tAW
tWR
tEW
tDW
DATAIN
VALID
tAS
tWP
tDH
tSAA
tOH
VALID ADDRESS
tACE
tSOP
DATAOUT
VALID(2)
tSWRD
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
tAOE
3039 drw 09
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
A0"B"-A2"B"
SIDE(2) "B"
R/W"B"
tSPS
MATCH
SEM"B"
3039 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port Amay be either left or right port. Port Bis the opposite from port A.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
61.402
 

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