IDT70121L View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT70121L Datasheet PDF : 16 Pages
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IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Timing Waveform of Interrupt Mode(1)
ADDR'A'
tWC
INTERRUPT SET ADDRESS(2)
tAS(3)
tWR(4)
R/W'A'
INT'B'
tINS (3)
Industrial and Commercial Temperature Ranges
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2654 drw 13
Truth Tables
Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
CE
OE
D0-8
Function
X
H
X
Z
Port Disab le and in Power-Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = H, Power-DownMode, ISB1 or ISB3
L
L
X
DATAIN Data on Port Written Into Memory(2)
H
L
L
DATAOUT Data in Memory Output on Port(3)
H
L
H
Z
High-Impedance Outputs
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
2654 tbl 13
Truth Table II. Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL
A10L-A0L
INTL
R/WR
L
L
X
7FF
X
X
X
X
X
X
X
X
X
X
X
X
L(3)
L
X
L
L
7FE
H(2)
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Right Port
CER
OER
A10R-A0R
X
X
X
L
L
7FF
L
X
7FE
X
X
X
INTR
Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
2654 tbl 14
13
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