IDT70121S45JG(2006) View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT70121S45JG
(Rev.:2006)
(Rev.:2006)
Integrated Device Technology
IDT70121S45JG Datasheet PDF : 15 Pages
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IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
Write Cycle Time (4)
25
____
35
____
ns
tEW
Chip Enable to End-of-Write
20
____
30
____
ns
tAW
Address Valid to End-of-Write
20
____
30
____
ns
tAS
Address Set-up Time
tWP
Write Pulse Width(6)
0
____
0
____
ns
20
____
30
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1,2,3)
tDH
Data Hold Time(5)
tWZ
Write Enable to Output in High-Z(1,3)
tOW
Output Active from End-of-Write(1,2,3,5)
12
____
20
____
ns
____
10
____
15
ns
0
____
0
____
ns
____
10
____
15
ns
0
____
0
____
ns
2654 tbl 10a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time(4)
45
____
55
____
ns
tEW
Chip Enable to End-of-Write
35
____
40
____
ns
tAW
Address Valid to End-of-Write
35
____
40
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
tWP
Write Pulse Width(6)
35
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
20
____
ns
tHZ
Output High-Z Time(1,2,3)
tDH
Data Hold Time(5)
____
20
____
30
ns
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z(1,3)
____
20
____
30
ns
tOW
Output Active from End-of-Write(1,2,3,5)
0
____
0
____
ns
NOTES:
2654 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
4. 'X' in part numbers indicates power rating (S or L).
5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions.
Although tDH and tOW values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW.
6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
6.842
APRIL 05, 2006
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