IDT70121S45JG View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT70121S45JG

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

Integrated Device Technology 

IDT70121/IDT70125

High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

tWC

ADDRESS

tHZ (7)

OE

CE

R/W

tAS(6)

tAW

tWP (2)

tWR(3)

tHZ (7)

DATAOUT

DATAIN

tWZ (7)

(4)

tOW

(4)

tDW

tDH

2654 drw 07

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)

tWC

ADDRESS

CE

tAS(6)

tAW

tEW (2)

tWR(3)

R/W

tDW

tDH

DATAIN

2654 drw 08

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be

placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short

as the specified tWP.

9

APRIL 05, 2006

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