IDT70121S45JG View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT70121S45JG
Integrated Device Technology
IDT70121S45JG Datasheet PDF : 15 Pages
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IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range(6)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
BUSY TIMING (For MASTER IDT70121)
Parameter
Min.
Max.
Min.
Max. Unit
tBAA
BUSY Access Time from Address
____
20
____
20
ns
tBDA
BUSY Disable Time from Address
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
tAPS
Arbitration Priority Set-up Time(2)
____
20
____
20
ns
50
60
35
45
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY INPUT TIMING (For SLAVE IDT70125)
tWB
Write to BUSY Input(4)
tWH
Write Hold After BUSY(5)
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
30
____
30
ns
15
____
20
____
ns
0
____
0
____
ns
15
____
20
____
ns
____
50
____
60
ns
____
35
____
45
ns
2654 tbl 11a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
BUSY TIMING (For MASTER IDT 70121)
Parameter
Min.
Max.
Min.
Max. Unit
tBAA
BUSY Access Time from Address
____
20
____
30
ns
tBDA
BUSY Disable Time from Address
____
20
____
30
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
30
ns
tBDC
BUSY Disable Time from Chip Enable
tWDD
Write Pulse to Data Delay(1)
____
20
____
30
ns
70
80
tDDD
Write Data Valid to Read Data Delay(1)
55
65
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY INPUT TIMING (For SLAVE IDT 70125)
tWB
Write to BUSY Input(4)
tWH
Write Hold After BUSY(5)
____
35
____
45
ns
20
____
20
____
ns
0
____
0
____
ns
20
____
20
____
ns
tWDD
Write Pulse to Data Delay(1)
____
70
____
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
55
____
65
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
2654 tbl 11b
61.402
APRIL 05, 2006
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