HD74HC563 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HD74HC563 Datasheet PDF : 11 Pages
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HD74HC563, HD74HC573
Octal Transparent Latches (with 3-state outputs)
REJ03D0629-0200
(Previous ADE-205-509)
Rev.2.00
Mar 30, 2006
Description
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and
the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of
the storage elements.
Features
• High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC563P
HD74HC573P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HC563FPEL
SOP-20 pin (JEITA)
HD74HC573FPEL
PRSP0020DD-B
(FP-20DAV)
FP
HD74HC563RPEL
PRSP0020DC-A
SOP-20 pin (JEDEC)
HD74HC573RPEL
(FP-20DBV)
RP
HD74HC573TELL TSSOP-20 pin
PTSP0020JB-A
T
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
Outputs
Output Control
Latch Enable
Data
HD74HC563
HD74HC573
L
H
H
L
H
L
H
L
H
L
L
L
X
Q0
Q0
H
X
X
Z
Z
Q0 : level of Q before the indicated Steady-sate input conditions were established.
Q0 : complement of Q0 or level of Q before the indicated Steady-state input conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 10
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