HD404328US View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

HD404328US

4-bit HMCS400-series microcomputer

Renesas Electronics 

HD404328 Series

Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register

(TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The

eight-bit configuration consists of lower and upper digits located at sequential addresses. A block diagram

of timer B is shown in figure 27.

Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower nibble must

be written to first. The contents of TLR are loaded into the timer counter at the same time the upper nibble

is written to, initializing the timer counter. TLR is initialized to $00 by MCU reset.

The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first;

the count is latched when the upper nibble is read. An auto-reload function, input clock source, and

prescaler division ratio of timer B depend on the state of timer mode register B (TMB). When an external

event input is used as the input clock source of TMB, the D8/ZCD/EVENT pin must be set to function as

the ZCD or EVENT pin by setting port mode register B (PMRB: $011).

Timer B is initialized to the value set in TMB by software, and is then incremented by one by each clock

input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if

the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the

timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0).

Interrupt request

flag of timer B

(IFTB)

EVENT

Clock

Free-running/

reload timer

control signal

Selector

Timer latch

register B

(TLB)

Timer/counter B

(TCB)

Overflow

Timer load

register B upper

(TLRU)

Timer load

register B lower

(TLRL)

3

System

clock

ø PER

Prescaler S (PSS)

Timer mode

register B

(TMB)

Figure 27 Timer B Free-Running and Reload Operation Block Diagram

46

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