HD404328UH View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

HD404328UH

4-bit HMCS400-series microcomputer

Renesas Electronics 

HD404328 Series

Timers

The MCU has two prescalers (S and W) and three timer/counters (A, B, and C).

Prescaler S: Eleven-bit counter that inputs a system clock signal. After being initialized to $000 by MCU

reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes,

and at MCU reset. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C input

clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode register

B (TMB), timer mode register C (TMC), and the serial mode register (SMR).

Prescaler W: Five-bit counter that inputs the X1 input clock signal divided by eight. Prescaler W output

can be selected as a timer A input clock by timer mode register A (TMA).

Timer A: Eight-bit timer that can be used as a clock time-base (figure 26). It is initialized to $00 and

incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an

overflow that sets the timer A interrupt request flag (IFTA: $001, bit 2) is generated, and timer A restarts

from $00.

Timer A is used to generate regular interrupts (every 256 clocks) for measuring times between events. It

can also be used as a clock time-base when bit 3 of timer mode register A (TMA) is set to 1. The timer is

driven by the 32-kHz oscillator clock frequency divided by prescaler W, and the clock input to timer A is

controlled by TMA. In this case, prescaler W and timer A can be initialized to $00 by software.

32.768-kHz

oscillator

1/4

1/2

f W Prescaler W

twcyc

(PSW)

2 fW

1/2 twcyc

Selector

Timer A interrupt

request flag

(IFTA)

Clock Timer

counter A

(TCA) Overflow

Selector

System

clock

ø PER

Prescaler S (PSS)

3

Timer mode

register A

(TMA)

Figure 26 Timer A Block Diagram

45

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