HD404328UFS View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HD404328UFS Datasheet PDF : 96 Pages
| |||
HD404328 Series
VCC
Pull-up
MOS
transistor
VCC
PMOS (A)
PMRC3
DCR
NMOS (B)
PDR
Input control
Input data
Table 23
Figure 25 I/O Buffer Configuration
Programmable I/O Circuits
PMRC, Bit 3
0
1
DCR
PDR
0
1
0
1
0
1
0
1
0
1
0
1
CMOS
Buffer
PMOS (A)
NMOS (B)
Off
Off
Off
On
Off
Off
Off
On
Off
Off
On
Off
Off
Off
On
Off
Pull-Up MOS Transistor
Off
Off
Off
Off
Off
On
Off
On
Notes:
1. Various I/O methods can be selected by different combinations of settings of the above mode
registers (PMRC3, DCR, PDR).
2. The PMOS (A) transistor of the R12 /SO pin can be turned off by setting bit 2 of the
miscellaneous register (MIS) to 1.
MIS R12 /SO Pin
Bit 2 PMOS (A)
0
On
1
Off
3. The relationships between DCRs and pins
are as shown on the right.
DCR
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCRB
DCRC
DCRD
Bit 3
R03
R13
R23
R33
R43
R53
D3
D7
—
Bit 2
R02
R12
R22
R32
R42
R52
D2
D6
—
Bit 1
R0 1
R1 1
R2 1
R3 1
R4 1
R5 1
D1
D5
—
Bit 0
R0 0
R1 0
R2 0
R3 0
R4 0
R5 0
D0
D4
D8
44
|
|
Share Link: 