FT2232H View Datasheet(PDF) - Future Technology

Part Name

Description

Manufacturer

FT2232H

Dual High Speed USB to Multipurpose UART/FIFO IC

Future Technology 

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Version 2.21

Clearance No.: FTDI#77

4.9 CPU-style FIFO Interface Mode Description

CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT2232H. This mode

is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit

(A0). When either Channel A or Channel B are in CPU-style Interface mode the IO signal lines are

configured as given in Table 3.10.

This mode uses a combination of CS# and A0 to determine the operation to be carried out. The following

truth-table, Table 4.7, gives the decode values for particular operations.

CS#

A0

RD#

WR#

1

X

X

X

0

0

Read Data Pipe

Write Data Pipe

0

1

Read Status

Send Immediate

Table 4.7 CPU-Style FIFO Interface Operation Select

The Status read is shown in Table 4.8

Data Bit

Data

Status

bit 0

1

Data available (=RXF)

bit 1

1

Space available (=TXE)

bit 2

1

Suspend

bit 3

1

Configured

bit 4

X

X

bit 5

X

X

bit 6

X

X

bit 7

X

X

Table 4.8 CPU-Style FIFO Interface Operation Read Status Description

Note that bits 7 to 4 can be arbitrary values and that X= not used.

The timing of reading and writing in this mode is shown in Figure 4.17 and Table 4.9.

A0

Valid

Valid

CS#

WR#

RD#

D7..0

t3

t1

t4

t6

Valid

Valid

t2

t5

t7

Figure 4.17 CPU-Style FIFO Interface Operation Signal Waveforms.

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