EP7312-IB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

EP7312-IB

High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface

Cirrus Logic 

Static Memory Single Write Cycle

EP7312

High-Performance, Low-Power System on Chip

EXPCLK

nCS

A

nMWE

tCSd

tAd

tMWd

tCSh

tMWh

nMOE

HALF-

WORD

WORD

D

EXPRDY

tHWd

tWDd

tDv

tEXs

tEXh

WRITE

Figure 8. Static Memory Single Write Cycle Timing Measurement

Note:

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is

sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period

where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with

valid timing under zero wait state conditions.

3. Address, Data, Halfword, Word, and Write hold state until next cycle.

DS508F1

©Copyright Cirrus Logic, Inc. 2005

(All Rights Reserved)

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