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DM74S280 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
DM74S280
Fairchild
Fairchild Semiconductor Fairchild
DM74S280 Datasheet PDF : 5 Pages
1 2 3 4 5
Logic Diagram
Typical Applications
Three DM74S280s can be used to implement a 25-line
parity generator/checker. This arrangement will provide
parity in typically 25 ns. (See Figure 1.)
Longer word lengths can be implemented by cascading
DM74S280s. As shown in Figure 2, parity can be gener-
ated for word lengths up to 81 bits in typically 25 ns.
FIGURE 1. 25-Line Parity/Generator Checker
FIGURE 2. 81-Line Parity/Generator Checker
www.fairchildsemi.com
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