DM74S112CW View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
DM74S112CW
Fairchild Semiconductor
DM74S112CW Datasheet PDF : 4 Pages
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August 1986
Revised April 2000
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74S112
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L
H
X
XX
H
L
H
L
X
XX
L
H
L
L
X
XX
H*
H*
H
H
H
H
H
H
H
H
↓
LL
Q0
Q0
↓
HL
H
L
↓
LH
L
H
↓
HH
Toggle
H
H
H
XX
Q0
Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level of Q before the indicated input conditions were
established.
* = This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006459
www.fairchildsemi.com
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