CY7C006 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C006 Datasheet PDF : 16 Pages
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Switching Waveforms (continued)
Read Timing with Port-to-Port Delay (M/S=L)[19, 20]
ADDRESSR
tWC
MATCH
R/W R
tPWE
DATA INR
tSD
tHD
VALID
ADDRESSL
DATAOUTL
MATCH
tWDD
tDDD
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]
tWC
ADDRESS
SEM OR CE
R/W
tSCE
tAW
tPWE
tSA
DATA IN
tHA
tSD
tHD
DATA VALID
CY7C006
CY7C016
VALID
C006-12
OE
DATA OUT
tHZOE
HIGH IMPEDANCE
tLZOE
C006-13
Notes:
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the
specified tPWE.
23. R/W must be HIGH during all address transitions.
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