CY7C006 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C006 Datasheet PDF : 16 Pages
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Pin Configurations (continued)
80-Pin TQFP
Top View
CY7C006
CY7C016
NC
1
I/O 2L
2
I/O 3L
3
I/O 4L
4
I/O 5L
5
GND
6
I/O 6L
7
I/O 7L
8
V CC
9
NC
10
GND
11
I/O0R
12
I/O1R
13
I/O2R
14
V CC
15
I/O 3R
16
I/O 4R
17
I/O 5R
18
I/O 6R
19
NC
20
Pin Definitions
Left Port
I/O0L–7L(8L)
A0L–13L
CEL
OEL
R/WL
SEML
Right Port
I/O0R–7R(8R)
A0R–13R
CER
OER
R/WR
SEMR
INTL
BUSYL
M/S
VCC
GND
INTR
BUSYR
CY7C016
60
NC
59
A5L
58
A4L
57
A3L
56
A2L
55
A1L
54
A0L
53
INTL
52
BUSYL
51
GND
50
M/S
49
BUSYR
48
INTR
47
A0R
46
A1R
45
A2R
44
A3R
43
A4R
42
NC
41
NC
C006-4
Description
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O0 pin is used when writing to a
semaphore. Semaphores are requested by writing a 0 into the respective
location.
Interrupt Flag. INTL is set when right port writes location 3FFE and is
cleared when left port reads location 3FFE. INTR is set when left port writes
location 3FFF and is cleared when right port reads location 3FFF.
Busy Flag
Master or Slave Select
Power
Ground
3
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