Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37128V
80
70
H igh S p eed
60
Low Power
50
40
30
20
10
0
0
20
40
60
80
100
120
140
Frequency (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37192V
120
H ig h S p e e d
100
80
Low Power
60
40
20
0
0
20
40
60
80
100
120
Frequency (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *D
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