Typical 3.3V Power Consumption
CY37032V
30
25
20
Ultra37000 CPLD Family
Low Power
High Speed
15
10
5
CY37064V
0
0
45
40
35
30
25
20
15
10
5
0
0
20
40
60
80
100
120
140
160
Frequency (MHz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
H igh Speed
Low Power
20
40
60
80
100
120
140
Frequency (MHz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *D
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