5962-9952102QYA View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
5962-9952102QYA Datasheet PDF : 64 Pages
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Ultra37000 CPLD Family
Parameter[11]
tER(–)
tER(+)
VX
1.5V
2.6V
Output Waveform—Measurement Level
VOH
0.5V
VX
0.5V
VX
VOL
tEA(+)
1.5V
0.5V
VX
VOH
tEA(–)
Vthe
VX
0.5V
VOL
(d) Test Waveforms
Switching Characteristics Over the Operating Range [12]
Parameter
Description
Combinatorial Mode Parameters
tPD[13, 14, 15]
tPDL[13, 14, 15]
tPDLL[13, 14, 15]
tEA[13, 14, 15]
tER[11, 13]
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
Input Register Parameters
tWL
Clock or Latch Enable Input LOW Time[8]
tWH
Clock or Latch Enable Input HIGH Time[8]
tIS
Input Register or Latch Set-up Time
tIH
tICO[13, 14, 15]
tICOL[13, 14, 15]
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
Synchronous Clocking Parameters
tCO[14, 15]
tS[13]
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
tH
tCO2[13, 14, 15]
Register or Latch Data Hold Time
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
tSCS[13]
tSL[13]
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0
CLK1, CLK2, or CLK3) or Latch Enable
tHL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,
CLK1, CLK2, or CLK3) or Latch Enable
Notes:
11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.
14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
15. When VCCO = 3.3V, add t3.3IO to this spec.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-03007 Rev. *D
Page 17 of 64
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