Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37384V
200
180
160
140
Low Power
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
Frequency (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37512V
250
H igh S p ee d
80
90
H ig h S p e e d
200
150
Low Power
100
50
0
0
10
20
30
40
50
60
70
80
90
Frequency (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *C
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