Typical 5.0V Power Consumption (continued)
CY37512
600
500
Ultra37000 CPLD Family
High Speed
400
300
Low Power
200
100
0
0
20
40
60
80
100
120
140
160
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Typical 3.3V Power Consumption
CY37032V
30
25
20
Low Power
High Speed
15
10
5
0
0
20
40
60
80
100
120
140
160
Frequency (MHz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *C
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