Typical 5.0V Power Consumption (continued)
CY37256
300
250
Ultra37000 CPLD Family
H igh Speed
200
Low Power
150
100
50
CY37384
0
0
20
40
60
80
100
120
140
160
180
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
500
450
400
350
300
250
200
150
100
50
0
0
Low Power
H igh Speed
20
40
60
80
100
120
140
160
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Document #: 38-03007 Rev. *C
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