Ultra37000 CPLD Family
Typical 5.0V Power Consumption (continued)
CY37128
160
140
H igh Speed
120
100
Low Power
80
60
40
20
CY37192
0
0
300
20
40
60
80
100
120
140
160
180
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
250
H igh S peed
200
150
Low Power
100
50
0
0
20
40
60
80
100
120
140
160
180
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Document #: 38-03007 Rev. *C
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